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3.0 Parallel Interface
The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its ad-
dressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1.
3.1 NON-MULTIPLEXED MODE
Non-multiplexed mode uses the control pins CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown
in Figure 4. This mode is selected by tying both the MODE1 and MODE0 pins to GND.
CS
A0
WR
RD
D7-0
The CPU has direct access to the DATA_IN, DATA_OUT and ADDR registers. Reading and writing data to the device can
be done either in standard access or burst mode. See Figure 5 for timing information.
CS
A0
RD
WR
D7-0
DATA_IN
DATA_OUT
ADDR
Figure 4. Non-Multiplexed Mode Block Diagram
Input
Write Address
Figure 5. Non-Multiplexed Mode Timing Diagram
13
0x00
Data In
Data Out
Address
0x3F
Out
Out
Read Data
Burst Read Data
Register File
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