Fifo Warning Mask Register (Fwmsk); Frame Number High Byte Register (Fnh); Frame Number Low Byte Register (Fnl) - NS USBN9603 Manual

7.0 Register Set
(Continued)
7.2.2

FIFO Warning Mask Register (FWMSK)

When set and the corresponding bit in the FWEV register is set, WARN in the MAEV register is set. When cleared, the cor-
responding bit in the FWEV register does not cause WARN to be set.
bit 7
0
7.2.3

Frame Number High Byte Register (FNH)

bit 7
MF
1
r
FN
Frame Number. This is the current frame number received in the last SOF packet. If a valid frame number is not received
within 12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change, the frame number is incre-
mented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next
frame number from a valid SOF packet.
If the frame number low byte was read by firmware before reading the FNH register, the user actually reads the contents of
a buffer register which holds the value of the three frame number bits of this register when the low byte was read. Therefore,
the correct sequence to read the frame number is: FNL, FNH. Read operations to the FNH register, without first reading the
Frame Number Low Byte (FNL) register directly, read the actual value of the three MSBs of the frame number. On reset, FN
is set to 0.
RFC
Reset Frame Count. Setting this bit resets the frame number to 0x000, after which this bit clears itself. This bit always reads
0.
UL
Unlock Flag. This bit indicates that at least two frames were received without an expected frame number, or that no valid
SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN.
On reset, this flag is set to 1.
MF
Missed SOF Flag. This flag is set when the frame number in a valid received SOF does not match the expected next value,
or when an SOF is not received within 12060 bit times. On reset, this flag is set to 1.
7.2.4

Frame Number Low Byte Register (FNL)

This register holds the low byte of the frame number, as described above. To ensure consistency, reading this low byte caus-
es the three frame number bits in the FNH register to be locked until this register is read. The correct sequence to read the
frame number is: FNL, FNH. On reset, FN is set to 0.
bit 7
0
bit 6 bit 5 bit 4
Same Bit Definition as FWEV Register
0 0 0
bit 6 bit 5 bit 4
UL RFC Reserved
1 0
r w/r0
bit 6 bit 5 bit 4
0 0 0
bit 3 bit 2
0 0
r/w
bit 3 bit 2
- 0
-
bit 3 bit 2
FN7-0
0 0
r
37
bit 1 bit 0
0 0
bit 1 bit 0
FN10-8
0 0
r
bit 1 bit 0
0 0
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