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3.0 Parallel Interface
3.2 MULTIPLEXED MODE
Multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE and the bidirectional address data
bus AD7-0 as shown in Figure 6. This mode is selected by tying MODE1 to GND and MODE0 to V
into the ADDR register when ALE is high. Data is output/input with the next active RD or WR signal. All registers are directly
accessible in this interface mode.
Figure 7 shows basic timing of the interface in Multiplexed mode.
CS
WR
RD
AD7-0
ALE
RD or WR
(Continued)
ADDR
EN
Figure 6. Multiplexed Mode Block Diagram
ALE
CS
AD7-0
ADDR
Figure 7. Multiplexed Mode Basic Read/Write Timing
Data In
Data Out
Address
DATA
15
. The address is latched
CC
0x00
0x3F
Register File
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