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8.0 Device Characteristics
D7-0 Input
Note: The setup and hold times t
Both signals may switch at the same time.
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01
(3.0V< V
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
CC
Symbol
t
ALE High Time
AH
t
Chip Select Low to ALE Low
CLAL
t
Address Valid to ALE Low
AVAL
t
Address Hold after ALE Low
AHAL
t
ALE Low to RD High
ALRH
t
Read Low to Data Valid
RDLV
t
Data Hold after Read High
RHDZ
t
Read Pulse Width
RL
t
Write High to next ALE High
WHAH
t
Write High to CS High
WHCH
t
Write Pulse Width
WL
t
Data Setup to WR High
DSWH
t
Data Hold after WR High
DHWH
1. Clock Internal: CKI = 48 MHz on this device
2. Memory Clock: MCLK = CKI/4 = 12 MHz
(Continued)
CS
A0
t
AS
t
WW
WR
t
DS
Valid
Figure 26. Non-Multiplexed Mode Write Timing
(Consecutive Write Cycles Shown)
and t
are defined relative to the first transition of either CS or WR.
AS
AH
)
B
Parameter
Conditions
C
= 50 pF
1
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
2
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
C
= 50 pF
L
t
AH
t
WC
t
DH
Valid
Min
Typ
1/CKI
1/CKI
10
10
3/MCLK
20
2
1/CKI
3/MCLK
10
1/CKI
5
5
55
Max
Units
nS
nS
nS
nS
nS
30
nS
nS
nS
nS
nS
nS
nS
nS
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