Clock Configuration Register (Cconf); Revision Identifier (Rid) - NS USBN9603 Manual

7.0 Register Set
(Continued)
7.1.2

Clock Configuration Register (CCONF)

bit 7
CODIS
0
r/w
CLKDIV
External Clock Divisor. The power-on reset and a hardware reset configure the divisor to 11
a 4 MHz output clock.
frequency = 48 MHz / (CLKDIV+1)
If the CLKDIV value is changed by firmware, the clock output is expanded/shortened if the CLKDIV value is increased/de-
creased in its current phase, to allow glitch-free switching at the CLKOUT pin.
CODIS
Clock Output Disable. Setting this bit disables the clock output. The CLKOUT output signal is frozen in its current state and
resumes with a new period when this bit is cleared.
7.1.3

Revision Identifier (RID)

This register holds the binary encoded chip revision.
bit 7
REVID
Revision Identification. For revision 9603 Rev A and 9604 Rev A, the field contains 0010
Table 5. Interrupt Output Control Bits
INTOC
1 0
0 0 Disabled
0 1 Active low open drain
1 0 Active high push-pull
1 1 Active low push-pull
bit 6 bit 5 bit 4
Reserved
-
-
bit 6 bit 5 bit 4
Reserved
-
-
Interrupt Output
bit 3 bit 2
CLKDIV3-0
1 0
r/w
bit 3 bit 2
REVID3-0
0 0
r
31
bit 1 bit 0
1 1
(decimal format), which yields
d
bit 1 bit 0
1 0
.
b
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