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5.0 MICROWIRE/PLUS Interface
The MICROWIRE/PLUS interface allows the device to function as a CPU or microcontroller peripheral via a serial interface.
This mode is selected by pulling the MODE1 pin high and the MODE0 pin low. The MICROWIRE/PLUS mode uses the chip
select (CS), serial clock (SK), serial data in (SI) and serial data out (SO) pins, as shown in Figure 14.
SYNC
SK
CS
SO
SI
5.1 OPERATING COMMANDS
The MICROWIRE/PLUS interface is enabled by a falling edge of CS and reset with a rising edge of CS. Data on SI is shifted
in after the rising edge of SK. Data is shifted out on SO after the falling edge of SK. Data is transferred from/to the Shift
register after the falling edge of the eighth SK clock. Data is transferred with the most significant bit first. Table 2 summarizes
the available commands (CMD) for the MICROWIRE/PLUS interface.
Note: A write operation to any register always reads the contents of the register after the write has occurred, and shifts out
that data in the next cycle. This read does not clear the bit in the respective registers, even for a Clear on Read (CoR) type
bit, with one exception: writing to the TXDx (transmit data) registers, which causes undefined data to be read during the next
cycle.
Byte Transferred
CMD
ADDR
1 0 5
4
3
0 0
RADDR
(read)
0 1
1 0
WADDR
(normal write)
1 1
WADDR
(burst write)
1. 1 cycle = 8 SK clocks. Data is transferred after the 8th SK of 1 cycle.
DATA_OUT
SHIFT
DATA_IN
ADDR
CMD1-0
Figure 14. MICROWIRE/PLUS Interface Block Diagram
Table 2. Command/Address Byte Format
Cycle
2
1
0
1
Shift in CMD/RADDR; shift out previous read data
2
Shift in next CMD/ADDR; shift out RADDR data
x
1
no action; shift out previous read data (do not clear CoR bits)
1
Shift in CMD/WADDR; shift out previous read data
2
Shift in WADDR write data; shift out WADDR read data (do
not clear CoR bits)
1
Shift in CMD/WADDR; shift out previous read data
2-n
Shift in WADDR write data; shift out WADDR read data (do
not clear CoR bits); terminate this mode by pulling CS high
Data Out
Data In
Address
1
Sequence Initiated
Description
19
0x00
0x3F
Register File
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