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CIRCUIT
DESCRIPTIONS
3-23
The
oiitput signal*
SGNOUT,
{output
1
B)
fs
fed to the
ADC.
The
voltage
range
of
SGNOUT
)s
1
,5V, ..3.5V,
The
Intermediate
level
of
SGNOUT
is
derived
irom
the
VREF
voltage
level,
which
is
made
by
the
ADC.
TRACK-
TRACK
TRACK
A-AS(C
(defiyM
TRACK-)
TRACK
i
^
HOLD
1
TRACK
SSNOin'
OT
A-ASIC
CLMADC
dalayed
.
>
:
oditf
1
HCUD
TRACK
1
TBATK
1
-An«
1
ADC
lakes
sample
'
Track
&
Hoid
timing
Externat Trigger Amplifier
This
amplifier section
prcxsesses the
incoming
external
trigger signal
so
that
it
can be used
in
the
trigger section.
The
Input of
this
section
is
TTL
compatible
Trigger Selector
In
this
section tne
channel
A,
channel
B
or external
trigger
input signal
is
selected
to
ad
as
trigger
source.
The
trigger
slope
is
also selected
in
this
block.
Hysteresis
The
hysteresis section converts the
trigger signal
into
a
pulse
shaped
signal.
Because
of
the
hysteresis,
the
circuit
will
not
trigger
on
noisy
signals.
The
LEVEL
signal (input
20)
that
determines
the
trigger
level>
Is
a
DC
voltage
between +0.5V and
+2.0V.
The
LEVEL
signal
Is
a
DC
voltage,
generated
in
the
Digital
ASIC.
Resistor
R2309
and
capacitors
C2312 andC2313
form
alowpass
filter,
to
convert
a pulse
width
modulated
signal
into
the
DC
voltage.
Detta^T
circuit
The
Delta-T
circuit
measures
the lime
between
a
trigger
pulse
and
the
moment
the
input signal
is
sampled.
Figure
3.14
shows
the timing
diagram
with relaton
to
the
signal
HLDF
(Input
1
0),
START
(internal),
STOPN
(output
9),
and
TOUT
(output
15).
1$}
ir<3
clocX
CtOCA
START:
Internal
(in
the
A-ASIC)
start
signal
for
the Delta-T
measurement.
TOUT:
a
voltage proportional
to
the
measured
value
(time)
of
Delta
T.
Figure 3.14 Timing
diagram Delta-T
circuH
Control
logic
The
control logic
section contains
a
serial-ln
parallel-out
shift
register.
This section gets
Its
data from
the
microprocessor (D1
201,
circuit
diagram A1.
figure
10.2) viafrie
CDAT
(serial
data),
CCLK
(sertd
clock),
and
DTAE
(data-latch)
lines.
The
control logic
section controls
ail
functional
blocks
within
ttie
A-ASIC,
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