Advantech ARK-5420 Series User Manual page 71

Intel 3rd generation core i processor based fanless system with pcie x 4 & pci slot
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outportb(SMBUS_PORT + 2, 0x48);// Write SMBUS command to
SMB_BASE + 2. 0x48 means starting byte data transmission.
moredelay();//longer delay
moredelay();//longer delay
for (i = 0; i <= 0x100; i++)
{
newiodelay();//longer delay
}
chk_smbus_ready();//?Whether SMBUS is ready
}
//////////////////////////////////////////////////////////////
///////////////////////////////////////
int
chk_smbus_ready()
//To decide whether SMBUS is ready or has completed the action,
you should wait for a long time to check whether SMBUS has
successfully transmitted the command. Since error may rarely
occurs, BIOS code does not make judgement on the return value
of this function in read and write of SUMBUS byte.
{
int i, result = 1;
BYTE data;
for (i = 0; i <= 0x800; i++)
{
//SMB_BASE + 0 is SMBUS status value
data = inportb(SMBUS_PORT);//Read
value once
data = check_data(SMBUS_PORT);//Read
value several timesoutportb(SMBUS_PORT, data);//?Write
SMBUS status value which will clear status value (Write 1 to
the corresponding bit means clearing status)
if (data & 0x02)
{
//If bit 1 is set (which means the command is
completed), SMBUS is ready
result = 0;//SMBUS ready
break;
}
if (!(data & 0xBF))
{
//If all bits are 0 except bit 2 (which means
error occurs on SMBUS), SMBUS is ready
result = 0;//SMBUS ready
break;
}
59
SMBUS
status
SMBUS
status
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ARK-5420 User Manual

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