Advantech ARK-5420 Series User Manual page 70

Intel 3rd generation core i processor based fanless system with pcie x 4 & pci slot
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outportb(SMBUS_PORT + 3, offset);// Write register off-
set to SMB_BASE + 3
newiodelay();//delay
newiodelay();//delay
outportb(SMBUS_PORT + 2, 0x48);// Write SMBUS command to
SMB_BASE + 2. 0x48 means starting byte data transmission
newiodelay();//delay
newiodelay();//delay
for (i = 0; i <= 0x100; i++)
{
}
chk_smbus_ready();//Whether SMBUS is ready
return(inportb(SMBUS_PORT + 5));// Byte value read from
SMB_BASE + 5
}
//////////////////////////////////////////////////////////////
///////////////////////////////////////
void
smbus_write_byte(BYTE addr, BYTE offset, BYTE value)
// Write SMBUS Register byte value. Write one byte value each
time. addr is slave address (such as 0x40), and offset is
register offset.
{
int i;
outportb(SMBUS_PORT + 4, addr);// Write slave address to
SMB_BASE + 4 (When writing, slave address bit 0 should be set
as 0)
moredelay();//longer delay
moredelay();//longer delay
chk_smbus_ready();//Whether SMBUS is ready
outportb(SMBUS_PORT + 3, offset);// Write register off-
set to SMB_BASE + 3
moredelay();//longer delay
moredelay();//longer delay
outportb(SMBUS_PORT + 5, value);//Write
SMB_BASE + 5
moredelay();//longer delay
moredelay();//longer delay
ARK-5420 User Manual
newiodelay();//longer delay
58
data
value
to

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