Table 6.2: Command Byte - Advantech ARK-5420 Series User Manual

Intel 3rd generation core i processor based fanless system with pcie x 4 & pci slot
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Below is the diagram of PCA9554 register:

Table 6.2: Command Byte

Command
Protocol
0
read byte
1
read/write byte
2
read/write byte
3
read/write byte
The command byte is the first byte to follow the address byte during a write transmis-
sion. It is used as a pointer to determine which of the following registers will be writ-
ten or read.
PCA9554 has in all 4 registers to control GPIO.
Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regard-
less of whether the pin is defined as an input or an output by Register 3. Writes to this
register have no effect.
The default 'X' is determined by the externally applied logic level, normally '1' when
no external signal externally applied because of the internal pull-up resistors.
Table 6.3: Register 0 - Input Port Register Bit Description
Bit
Symbol
Access
7
I7
read only
6
I6
read only
5
I5
read only
4
I4
read only
3
I3
read only
2
I2
read only
1
I1
read only
0
I0
read only
If one GPIO Pin is set to Input, you can read input value from the bit that register 0
corresponds to.
Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Regis-
ter 3. Bit values in this register have no effect on pins defined as inputs. Reads from
this register return the value that is in the flip-flop controlling the output selection, not
the actual pin value.
Table 6.4: Register 1 - Output Port Register Bit Description
Bit
Symbol
Access
7
O7
R
6
O6
R
5
O5
R
4
O4
R
3
O3
R
2
O2
R
1
O1
R
0
O0
R
Function
Input Port register
Output Port register
Polarity Inversion register
Configuration register
Value
Description
X
X
X
X
determined by externally applied logic level
X
X
X
X
Value
Description
1*
1*
1*
reflects outgoing logic levels of pins defined as outputs by
1*
Register 3
1*
1*
1*
1*
55
ARK-5420 User Manual

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