Retu Em Asic; Tahvo Em Asic; Device Memories; Rap3G Memories Nor Flash And Sdram - Nokia 6680 RM-36 Service Manual

RM-36
System Module Nokia Customer Care
In general RAP3G consists of three separate parts:
• Processor subsystem (PSS) that includes the main processor and related functions
• MCU peripherals that are mainly controlled by MCU
• DSP peripherals that are mainly controlled by DSP
RAP3G core voltage (1.40V) is generated from Tahvo VCORE and I/O voltage (1.8V) is from Retu VIO. The core
voltage in sleep mode is lowered to 1.05V.

Retu EM ASIC

Retu EM ASIC includes the following functional blocks:
• Start up logic and reset control
• Charger detection
• Battery voltage monitoring
• 32.768kHz clock with external crystal
• Real time clock with external backup battery
• SIM card interface
• Stereo audio codecs and amplifiers
• A/D converter
• Regulators
• Vibra interface
• Digital interface (CBUS)

Tahvo EM ASIC

Tahvo EM ASIC includes the. following functional blocks:
• Core supply generation
• Charge control circuitry
• Level shifter and regulator for USB/FBUS
• Current gauge for battery current measuring
• External LED driver control interface
• Digital interface (CBUS)

Device memories

RAP3G memories NOR flash and SDRAM

Modem memory consists of 64 Mbit SDRAM and 64 Mbit NOR flash memories.
SDRAM is a dynamic memory for ISA SW.
NOR is used for ISA SW code and PMM data and CDSP SW code.
16-bit wide SDRAM interface consists of DDR SDRAM controller from ARM, DCDL/DLLs and wrapper logic. 32-bit
wide flash interface is implemented by using EMC module.
SDRAM core voltage (1.8V) is generated from Retu VDRAM and I/O voltage (1.8V) is from VIO. NOR flash uses VIO
for both core and I/O voltages.
Issue 1 Company Confidential Page 9–25
Copyright ©2005 Nokia. All Rights Reserved.