Advantech PCM-4862 Manual page 80

All-in-one 486 single board computer with svga, ethernet, and ssd
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Jumpers J23 and J24 control the watchdog settings. The default
configuration of the timer is enabled with system reset.
To enable the watchdog timer, you must write a program which
reads I/O port address 443 (hex) at regular intervals. The first time
your program reads the port, it enables the watchdog timer. After
that, your program must read the port at time interval of less than
1.6 seconds, otherwise the watchdog timer will activate and reset
the CPU or generate an interrupt on IRQ15. When you want to
disable the watchdog timer, your program should read I/O port 043
(hex).
If CPU processing comes to a standstill because of EMI or a
software bug, your program's signals to I/O port address 443 to the
timer will be interrupted. The timer will then automatically reset
the CPU or invoke an IRQ, and data processing will continue
normally.
You must write your program so that it reads I/O port address 443
at an interval shorter than the timer's preset interval. The timer's
intervals have a tolerance of ±30%, so you should program an
instruction that will refresh the timer about every second.
The following program shows how you might program the
watchdog timer in BASIC:
10
REM
Watchdog timer example program
20
X=INP (&H443) REM
30
GOSUB 1000 REM
40
X=INP (&H443) REM
50
GOSUB 2000 REM
60
X=INP (&H043) REM
70
END
1000
REM
Subroutine #1, takes 1 second to complete
.
.
.
1070
RETURN
2000
REM
Subroutine #2, takes 1 second to complete
.
.
.
2090
RETURN
72
PCM-4862 User's Manual
Enable and refresh the watchdog
Task #1, takes 1 second to complete
Refresh the watchdog
Task #2, takes 1 second to complete
Disable the watchdog

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