Table of Contents
Advertisement
Chapter 2 Programming Details
A hardware Flash bank write protect switch is provided on the MVME3100 to enable write protection of
both physical banks. Regardless of the state of the software Flash write protect bit in the Flash
Control/Status register, write protection is enabled for both banks when this switch is ON. When this
switch is OFF, write protection is controlled by the state of the software Flash write protect bit and can
only be disabled by clearing this bit in the Flash Control/Status register. Refer to
Register on page 12
Note
The F_WE_HW bit reflects the state of the switch and is only software readable, whereas the
F_WP_SW bit supports both read and write operations.
The MVME3100 provides a dual boot option for booting from one of two separate boot images in the
boot Flash bank, which are referred to as boot block A and boot block B. Boot blocks A and B are each
1MB in size and are located at the top (highest address) 2 MB of the boot Flash memory space. Boot
block A is located at the highest 1MB block and block B is the next highest 1MB block. A FLASH boot
block switch is used to select between boot block A and boot block B. When the switch is OFF, the Flash
memory map is normal and block A is selected. When the switch is ON, block B is mapped to the highest
address as shown below. The MAP_SEL bit in the Flash Control/Status register can override the switch
and restore the memory map to the normal configuration with block A selected. Upon RESET, this
mapping reverts to the switch selection.
PCI IDSEL Definition
Each PCI device has an associated address line connected via a resistor to its IDSEL pin for
configuration space accesses. The following table shows the IDSEL assignments for the PCI devices
and slots on each of the PCI buses on the board, along with the corresponding interrupt assignment to
the PIC external interrupt pins. Refer to the MPC8540 Reference Manual and PCI6520CB Data Book
and for details on generating configuration cycles on each of the PCI busses.
Table 2-7. IDSEL and Interrupt Mapping for PCI Devices
PCI Bus
A
(8540) (See Note
following table)
B
(PCI6520-1)
32
MVME3100 Programmer's Guide (V3100A/PG1)
for more information.
Device
AD Line
Number
for
PCI Device
Field
IDSEL
or Slot
0b0_0000
internal
MPC8540
0b0_0001
17
TSi148
VME
0b0_0010
18
PCI6520-1
0b0_0011
19
PCI6520-2
0b0_0100
20
GD31244
sATA
0b0_0000
16
PMC1
Primary
0b0_0001
17
PMC1
Secondary
Flash Control/Status
Device/Slot INT to MPC8540 Ext IRQ
INTA#
INTB#
INTC#
IRQ0
IRQ1
IRQ2
IRQ2
IRQ4
IRQ5
IRQ6
IRQ5
IRQ6
IRQ7
INTD#
IRQ3
IRQ7
IRQ4
Advertisement
Table of Contents
