Table 1-2. Local Bus Memory Map - Motorola MVME166IG/D2 Installation Manual

Address Range
$00000000 - DRAMSIZE
DRAMSIZE - $FF7FFFFF
$FF800000 - $FF8FFFFF
$FFC00000 - $FFDFFFFF
$FFE00000 - $FFE1FFFF
$FFE20000 - $FFEFFFFF
$FFF00000 - $FFFEFFFF
$FFFF0000 - $FFFFFFFF
NOTES:
1.
2.
3.
4.
5.
MVME166IG/D2

Table 1-2. Local Bus Memory Map

Devices Accessed Port Size
User Programmable
(Onboard DRAM)
User Programmable D32/D16
(VMEbus or VSB)
FLASH
reserved
SRAM
SRAM (repeated)
Local I/O Devices D32-D8
(Refer to next table)
User Programmable D32/D16
(VMEbus A16)
There is 1MB of FLASH in this 4MB map area. Download
EPROM on the MVME166 appears at $00000000 - ROMSIZE
following a local bus reset. The Download EPROM appears
at 0 until the DR0 bit is cleared in the PCCchip2. The DR0 bit
is located at address $FFF42000 bit 15. The EPROM must be
disabled at 0 before the DRAM is enabled. The VMEchip2,
VSBchip2, and DRAM map decoders are disabled by a local
bus reset.
This area is user-programmable. The suggested use is shown
in the table. The DRAM decoder is programmed in the
MCECC chip, and the local-to-VMEbus decoders are
programmed in the VMEchip2. The local-to-VSB decoders
are programmed in the VSBchip2.
Size is approximate.
Cache inhibit depends on devices in area mapped.
This area is not decoded. If these locations are accessed and
the local bus timer is enabled, the cycle times out and is
terminated by a TEA signal.
Software
Size Cache
Inhibit
D32 DRAMSIZE
3GB
D32 1MB
-- 2MB
D32 128KB
D32 896KB
1MB
64KB
Memory Maps
Notes
N 1, 2
? 3, 4
N 1
-- 5
N --
N --
Y 3
? 2, 4
1-19
1