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System Service
input voltage is removed, battery power is available for up to 90 minutes (depending on memory size
and battery condition) to maintain memory data and check bits. The volatile characteristics of a
dynamic MaS semiconductor memory dictates this back-up power requirement.
The memory module interfaces with other modules in the system through the Central Data Bus (CTL).
Other modules on this bus may request transfers of data to or from the memory modules. Operation of
the memory with other modules on the CTL bus is controlled by the MCV logic (module control unit)
on the MCL PCA. The MCL PCA checks all data on the CTL bus for correct parity during a write
operation and provides correct parity to the CTL bus during a read operation.
4-98.
ERROR CORRECTION
Error correction detects and corrects all single bit errors. Some multiple bit errors are detected, but not
corrected. Error checking and correcting occurs during the normal memory cycle of READ and RW1
operations only.
The FCA PCA adds a five bit check field (A,B,C,D,E) to each 16 bit memory word. The check bits are
actually parity bits calculated over specific bits of the data word. See figure 4-22 for the check bit
assignments.
DATA BITS
o
1 2 3 4
5 6
7 8
9
10 11
12 13 14 15
CHECK BITS
x x x x x x x
X
A even parity
X X
X
X
X X X
X
B odd parity
X
X X
X X
X
X
X
C even parity
X
X
X
X
X
X
X
X
D odd parity
X
X
X
X
X
X
X
X
E even parity
7522-52
Figure 4-22. Check Bit Assignments
During the WRITE operation, check bit A is stored in the SMA PCA 17th bit position where the data
parity bit would normally be stored in a non-error correcting memory system. Check bits B,C,D, and E
are stored on the FCA peA.
During the READ operation, parity is checked on the same data bits, and the check bits. If the
resulting error code (A',B',C',D' and E') calculation is zero, no error occurred in memory. If the error
code is other than zero, the appropriate error bit is toggled. Figure 4-23 shows the bit pattern and
check bits generated for a data word of
%
123456 during a WRITE and a READ operation. The figure
illustrates the check bits produced when no error occurs, the error code is equal to zero.
%123456
o
1 2
3
4
5 6
7 8 9
10 11
12 13 14 15
o
o
o
WRITE
READ
A B C D E
A' B' C' D' E'
Check Bits
Error Code
0
0
0
0
0
0
0
Figure 4-23. Check Bits and Error Code (No Error)
4-36
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