HP 3000 SERIES II System Service Manual page 97

Maintenance Procedures
4-24. Bits 6 and 7 - Control Code. These bits define how the two control words sent during
channel execution of a Control order are used. The normal mode loads the Control order lOAW into the
control register to be used as a control word. The other modes load either or both the 10CW and 10AW
into the counter/buffer leaving the control register contents unchanged.
4-25. Bit 8 - High Speed Service Request. This bit, if a ((I", overrides the SCMB service
request delay (normally 200kHz) to force continuous CHAN SR signals (when required) to the
channel. The resulting transfer rate will be approximately 950 kHz outbound and 1140 kHz inbound.
4-26. Bit 9 - Device Number. This bit, if a ((I", supplies the contents of the counter/buffer as
the device number at I/O program initiatioin instead of the hardwired device number. By preloading
the counter/buffer using a direct WIO instruction, an I/O program can be executed to any device
number.
4-27. Bit 10 - Terminate on Terminal Count. This bit, if a ((I", causes a Device End or clear
interface (ie, REQ) to be issued to the channel if the counter/buffer contents ((rollover" (ie, past count
capacity). Whether device end or clear interface is issued is determined by the state of bit 12.
4-28. Bit 11 - Terminate on NO Compare. This bit, if a ((I", causes the contents of the
counter/buffer to be compared to data words issued to the maintenance PCA during channel execution
of a Write order. (Normally, data received during execution of a Write order is loaded into the
counter/buffer. If bit 11 is a ((I", the counter/buffer contents remain unchanged.) If a compare failure
occurs, the SCMB issues either a Device End signal or a clear interface (ie, REQ) to the channel.
Whether device end or clear interface is issued is determined by the state of bit 12.
4-29. Bit 12 - Clear Interface. This bit, if a ((I", causes a clear interface (ie, REQ) to be issued
to the channel if either conditions controlled by bits 10 or 11 occur. If a ((I", a Device End signal is
issued if the bit 10 or 11 condition occurs.
4-30. Bit 13 - 15 - Counter/Buffer Operation. These bits control the operation of the counter/
buffer. When used as a buffer, the counter/buffer is loaded with data words received during channel
execution of a Write order (unless bit 11 is a ((I"). The buffer contents are sent to the channel as data
during channel execution of a Read order.
NOTE
Upon receipt of an I/O Reset signal, the SCMB counter/buffer and
control word storage registers are cleared Therefore, the initial
operating state of the SCMB is as follows:
1) the counter/buffer contents
=
((0"
2) if a Control order is executed, the Control order lOAW will be
used as a Control word
3) the SCMB wired device number will be sent if an SIO instruc-
tion is executed to the SCMB
4) the counter/buffer will be used as a buffer.
4-11