HP 3000 SERIES II System Service Manual page 123

Maintenance Procedures
Using the same data word (%123456), figure 4-24 illustrates the error code produced during a READ
operation when an error in memory drops bit O. The resulting error code (11100) is interpreted by table
4-8 as a fault in bit
o.
Before the data is presented on the CTL bus, bit 0 would be toggled, thereby
correcting the error. Note that the check bits generated in both figures are identical, this is because
the check bits are generated on the data bits before data is entered in memory.
%123456 WRITE READ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ABC D E A' B' C' D' E'
1 0 1 0 0 1 1 0 0 1
0 0
Check Bits
Error Code
1 0 1 0 0 1 1 1
1)
1 0 1 0 0 0 1 0 0
. /
0
1 0 1 0 0
. /
0
0 0 0 0 0
0 0 0 0
7522·54
Figure 4-24. Check Bits and Error Code (Error Condition)
To maintain system integrity, parity is checked on each word written into memory. If parity is wrong
on the CTL bus, it is indicated on the SYS PE line. In the error correcting memory, parity is generated
by the FCA PCA. When data is read from memory, parity is calculated from the field of data bits
(0 - 15). If an error is made on any data bit, parity is toggled along with the particular error bit.
Referring again to figure 4-24, the data read (0 010 011100 101110) would be modified to produce a
data word of 1 010 011 100 101 110 and a parity bit of
o.
If memory is operating as non-error correcting, parity is checked and written as received on the CTL
bus and the same value is placed on the bus during a read operation.
When errors are corrected, a logic ((I" is stored in a Error Logging Array (ELA) static 1K RAM located
on the MCL PCA. The RAM is organized in a 1024 X 1 bit array requiring 10 bits for addressing. The
five most significant bits of the address correspond to the bank bit 0 and four most significant bits of
the memory address that had an error bit. The five least significant bits of the error logging array
address correspond to the error code A' thru E'. Any error logging array location containing a ((I"
signifies an error was detected. The error logging array is read under program control by the FLI PCA.
Figure 4-25 illustrates the structure of the error logging array address for an error in bit 0 of memory
address 10000.
Figure 4-25 shows the formation of a 10-bit error logging address 0047. This address contains a logic
((I"
if bit 0 of system address 010000 through 017777 had been corrected. Address 010000 is located on
SMA PCA board 1, the memory chip is on row 1 (chip select line 1), the er:ror bit 0 will identify the
specific chip. The error logging array can record errors occurring on up to four SMA PCA'sand one
FCA PCA. An additional MCL PCA containing the error logging array and a FCA PCA must be
installed whenever memory size exceeds 128K words.
The FLI PCA under program control interrogates the error logging array in the MCL PCA approxi-
mately once each hour, however, this can be changed by running the program MEMTIMER (refer to
paragraph 4-99). If a logic
((I"
is detected in the array, the error address is read and decoded. An error
file is updated that can be accessed by the CE during PM intervals. The file will display information
pertaining to memory errors.
4-37