HP 3000 SERIES II System Service Manual page 148

System Service
The ReadlWrite Selector on the FCA PCA, figure 4-38, selects one of four drivers for reading or
writing, depending on the bit configuration of the ARO and AR1 signals. ARO and AR1 are formed in
the MCL Timing and Control Circuits and actually relate to the most significant bit of the address
word (AR1) and the bank register bit (ARO). This combination selects which sector of the FCA Memory
Array the check bits are written into or read from.
During a Read or RW1 operation, the 16 bits read from the SMA PCA are stored in the MCL Data
Register. The same 16 bit data word is also presented to the FCA Check Bit/Error Code Generator. In
addition, the 17th bit (CHECK BIT A) read from the SMA PCA is directly presented to the Check
Bit/Error Code Generator, not via the MCL Data Register. Simultanously, the four CHECK BITS
(B,C,D,E) are read from the same address in the FCA Memory Array and sent to the Check Bit/Error
Code Generator. A 5-bit Error Code is then generated from the 21 bits presented to the generator. This
ERROR CODE will be equal to zero if none of the 21 bits has changed, compared to the original bits
when the word was written and check bits were generated.
The ERROR CODE is then latched into the MCL Error Code Register and presented to the Error
Detector where the ERROR CODE is checked to see if it is equal to zero (00000). When it is equal to
zero, the Error Corrector does not modify the data bits from the MCL Data Register, and the data is
sent to the CTL Bus.
When the Error Detector checks the ERROR CODE and it is not equal to zero, the Error Corrector will
complement the bit in error which was determined by the ERROR CODE, and then send the data to
the CTL Bus. Only one error bit can be corrected in a data word. An ERROR signal is produced by the
Error Detector that activates the Read/Write Control Circuit and causes a ((1" to be written into the
Error Logging Array. Errors are only logged during Read and RW1 operations.
The address where the flag C(l") is written is determined by a 10-bit address that consists of the 5-bit
ERROR CODE, three bits of the address read (AD01-AD03) and the signals ARO and ARl. The fact
that an error occurred is represented by the ((1" stored in the Error Logging Array. The actual bits of
the address where that ((1" is stored represents information about the error.
The Error Logging Array is read by the FLI PCA only during Refresh time so as not to interfere or
extend the normal memory cycle.
4-124. FAULT LOGGING INTERFACE peA
The FLI PCA under software control reads from and writes into the MCL Error Logging Array (ELA).
The FLI PCA only operates with direct I/O commands received on the lOP Bus. All communication
between the MCL and FLI PCA's occurs on the Fault Logging Interface Bus. See figure 4-39.
Although the FLI PCA reads and writes the ELA, all logging information must pass through the FLI
110
Logging Array. Data is copied from the ELA into the I/O Logging Array, and then the I/O Logging
Array is read onto the lOP Bus. To write into the ELA, the
110
Logging Array is written into from the
lOP Bus, then the I/O Logging Array is read into the ELA. Writing into the ELA is normally done with
all zeros to clear the entry in the ELA.
Direct I/O instructions are decoded by the Command Decoder to the Timing Control Circuits and set
the R/NW Control Circuit to the appropriate condition for reading or writing. To perform a read of the
MCL ELA, that particular MCL PCA must be selected since the FLI PCA can service two independent
MCL PCA's. A starting address is loaded into the FLI Address Counter and is applied to the Address
Comparator and I/O Logging Array. The other input to the Address Comparator is the address of the
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