HP 3000 SERIES II System Service Manual page 137

Maintenance Procedures
4-113. ERROR CORRECTING MEMORY MODULE.
A typical error correcting memory module is shown in figure 4-33. The figure shows the major data
and signal paths between PCA's in the module.
During a write operation the addressed memory location is latched in the MCL Address Register and is
presented to the SMA and FCA Memory Arrays. The memory location in the SMA is therefore
accessed and the corresponding section in the FCA Memory Array is also accessed for storing the check
bits. Address parity is checked by the MCL Parity Generator/Checker and a parity error is sent on the
CTL bus if parity is incorrect. Data parity is also checked during a write operation and indicated on the
NSYS PE line.
Data is latched in the MCL Data Register and stored in the SMA Memory Array'. The data is also sent
to the FCA Check Bit/Error Code Generator to generate the check bits that are then stored in the FCA
Memory Array. Four of the check bits are stored in the FCA Memory Array and check bit A is stored in
the 17th bit position of the SMA Memory Array.
When a memory location is read, the data from the SMA Memory Array is latched in the MCL Data
Register and presented to the FCA Check Bit/Error Code Generator. The check bits that are simul-
taneously read out with the data are sent to the FCA Check Bit/Error Code Generator, and together
with the data bits form a five bit error code CA' - E').
The MCL Error Code Register stores this error code and presents it to the MCL Error Detector and the
Multiplexer. If the error code is equal to zero, data from the MCL Data Register is unchanged by the
MCL Error Corrector and gated to the CTL bus with parity which is calculated on the data bits.
When the error code is not equal to zero, the MCL Error Detector activates the appropriate output line
to the MCL Error Corrector and complements the bit in error. Parity is then calculated on the
corrected data bits and sent to the CTL bus with the data. When an error has been detected, the error
code along with the bank bit and four most significant bits CAO - A3) of the address containing the
error are formed into a ten-bit address by the MCL Multiplexer. With the error signal present, a
(~1"
is
written into the MCL Error Logging Array at the address specified by the Multiplexer. The ((I" written
into the array signifies that an error actually occurred. The bits of the address where that
(~1"
is stored
actually contain the information such as location, type of error, row and chip number where the error
occurred.
Under software control, direct I/O commands cause the FLI PCA to interrogate the MCL Error
Logging Array approximately once each hour to find out if an error has occurred. The Error Logging
Array is then copied into the FLI I/O Logging Array where it is then available to be sent on the lOP
bus. The starting address of the interrogation is loaded into the FLI Address Counter. This same
address is then applied to the I/O Logging Array and Address Comparator. When the MCL Refresh
Counter reaches the starting interrogating address, the FLI Address Comparator signals the R/W
Control circuit to read into the I/O Logging Array the contents of the Error Logging Array. The FLI
Address Counter increments along with the Refresh Counter to keep both addresses in sync.
When the interrogation is finished, the MCL Error Logging Array should be cleared to all zero's so
that repetitive errors can be logged. The I/O Logging Array is read by software and the data is stored
in a disc file. The I/O Logging Array can be written into the MCL Error Logging Array. Reading the
MCL Error Logging Array can only occur during refresh time. This prevents interference with a
normal memory operation, and does not extend the cycle time.
4-51