HP 3000 SERIES II System Service Manual page 176

System Service
The -20 volt supply and transistor A8Q2 comprise a series-type regulator, with the output voltage
determined by +20 volt output. Divider A3R28 and A3R29, and comparator A3U3 function as an
error signal generator and detector which causes the -20 volt output to equal and track the +20 volt
output. The error signal level is shifted by A3R7 and A3R21 and applied to A3U2. The output of
amplifier A3U2 is at the proper level to control the driver, which directly controls the current
through A8Q2. If the +20 and -20 volt outputs are not equal and opposite in polarity, error
amplifier A3U3 provides an error signal to correct the -20 volt output. If the -20 volt load current
is excessive, a current monitor circuit holds back the driver to protect A8Q2.
The DC voltage drops across the output filter chokes for +15, +5, -5, and -15 volt outputs are
monitored by current limiter PCA A4. Any excessive current (typically 15 percent above rated
value) results in the generation of an OVERCURRENT signal, which delays the firing angle
comparator circuit in PCA AI. This limits the blocking oscillator, which decreases the preregulator
output voltage, to protect the power supply. Thus, a current overload is reflected in lowered output
voltages on the ±5 and ±15 volt. The +5 volt current limit circuitry has the added capability of an
adjustable limit threshold. This circuitry protects external subsystems where overloads greater than
10 amperes may occur which do not exceed the rated capability of the power supply. The
overcurrent threshold for the +5 output is set by A4RI. An overcurrent condition must exist for at
least 2 seconds to set an overcurrent latch which activates the OVERCURRENT signal. Switch
A4S1 and light-emitting diode (led) A4CR7 are used by the operator to set the overcurrent
threshold 10 amperes above the operating current level. The switch is also used to reset the latch.
Instructions for this adjustment are printed on the power supply cover. Because of the abrupt
action of the overcurrent latch, all of the output voltages go to zero, whereas, the ±15 and -5
overcurrent circuits (described at the beginning of the paragraph) are protected by "foldback
current limiter" action only. The +20 and -20 volt outputs are individually protected by current
monitor circuits in the ±20 volt supply PCA A3.
All supply output voltages, except for the +20 volts, are monitored by overvoltage and undervoltage
comparators in voltage protect PCA A5. If an overvoltage condition is sensed, a latch is set via
A5CR4. When this occurs, the INU driver is enabled, and the INU signal goes low. With INU low,
the blocking oscillator in PCA Al and the phase divider circuit in A2 are disabled. This action
disables the preregulator and inverter, thus protecting the power supply when the crowbars are
fired. The latch output is also level-shifted and applied to a blocking oscillator which provides three
transformer-coupled crowbar trigger pulse outputs. The trigger pulses fire the 130-volt rail crowbar
and both output crowbars: the 130-volt rail, the +20 and -20 volt outputs, and the +5 and -5 volt
outputs are shorted. To reset the latch, the power supply must be turned off. A level detector
monitors the internal +15 and -15 volt biases and acts as a turn-on inhibit to the overvoltage latch
to prevent premature operation of the crowbars any time power is applied.
The Functional Timing Diagram in figure B-3 illustrates turn-on sequencing of the power supply.
When the power supply is turned on, the DC output voltages rise until the undervoltage
comparators provide
an
enable signal (PSU) to the PON circuit. Assuming PFW is up, a 0.6·second
delay is provided between PSU and PON. A comparator circuit monitors the secondary winding
voltage of T3. If the line voltage falls below a preset limit, comparator A5UIB provides a low LPU
signal. LPU is connected through a driver (A5U4B) to provide the PFW signal. If PFW should occur
before the 0.6 second delay in the PON circuit has elapsed, gate A5U4A resets the PON delay. A
high PFW signal has no effect once the PON signal is high. When the DCE signal goes high (open) or
an overtemperature condition inA6 is sensed, comparator A5UIA provides a low PFW signal
through A5CR12 and A5U4B. LPU goes low at the same time. After a delay of 12 ms, the INU
driver is enabled through A5CR9. The INU signal disables the preregulator and inverter. When DCE
B-14
JAN 1977