Table of Contents
Advertisement
Maintenance Procedures
•
To indicate whether the module is ready or not, READY (00-03)
•
To resolve priority considerations, ENABLE (00-03)
•
To select a specific memory operation, MOP(OO-Ol)
•
To indicate a parity error on transfer of control information and data parity error during a write
cycle, NSYS PE.
•
To indicate parity for the control lines, SYSPRTY
•
The ((not" master reset (NMCU RST) pulse initializes the MCL PCA during initial power turn-on
and during power failure. Control can be reset during a refresh cycle without loss of stored data.
•
To indicate an address parity error, NMCUD PE
4-110.
lOP BUS. The FLI PCA interfaces with the lOP bus to execr
Je
direct 110 commands. The
FLI PCAinterrogates the MCL fault logging array and stores the contents into the FLI 110 logging
array. Commands on the lOP bus then cause a read of the 110 logging array and transfer the contents
into a disc file for future analysis.
4-111.
FAULT LOGGING INTERFACE BUS. The fault logging interface bus is a flat cable
connected between P3 on the MCL PCA and P2 on the FLI PCA. All communication between these two
PCA's occurs on this bus. When a memory is configured above 128K words, this bus extends to P3 of
the upper 128K MCL PCA. A single FLI PCA can communicate independently over the bus to the
selected (upper or lower 128K) MeL PCA.
4-112.
POWER BUS. The CPU applies an ENTIMER signal to the MCL PCA via the power bus
to enable a timer during every write cycle. If the data is not received within 6.4 msec during a write
operation, the timer resets the control circuits to prevent memory from waiting for data. No loss of
memory data occurs during an incomplete write cycle.
System clock (NMCUCLK) is a 175 nsec square wave from the CPU that provides timing to the MCU
circuits. The NMCUCLK can be halted and pulsed for maintenance purposes with the single cycle
switch on the HP 30354A Maintenance Panel. For maintenance purposes, NMCUCLK can be discon-
nected and replaced with an external timing signal.
Refresh clock timing is automatically selected from an oscillator internal to the MCL PCA, or from the
NFRUNCLK signal input. NFRUNCLK is in sync with NMCUCLK, but cannot be halted with the
single-cycle switch.
Power failures are sensed in the HP 30310A Power Supply and initiate the NPF WARN (power fail
warning) to the CPU and memory. The MCL PCA guarantees 3.5 msec for the CPU to execute its
power fail routine and store the necessary information into memory. After this 3.5 msec interval, clock
timing to memory is disabled to prevent any further read or write operations until power is restored.
4-49
Advertisement
Table of Contents
