Intel 80331 Design Manual page 4

Intel® 80331 I/O Processor Design Guide
Contents
6.4.14 PCI 66 MHz Slot Topology .................................................................................... 60
6.4.15 PCI 66 MHz Embedded Topology ......................................................................... 61
6.4.16 PCI 66 MHz Mixed Mode Topology ....................................................................... 62
6.4.17 PCI 33 MHz Slot Topology .................................................................................... 63
6.4.18 PCI 33 MHz Embedded Mode Topology ............................................................... 64
6.4.19 PCI 33 MHz Mixed Topology ................................................................................. 65
7 Memory Controller....................................................................................................................... 67
7.1 DDR Bias Voltages ............................................................................................................. 67
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7.2 Intel 80331 I/O Processor DDR Overview ........................................................................ 68
7.3 DDR 333 Signal Integrity Simulation Conditions ................................................................ 69
7.3.1 DDR 333 Stackup Example ................................................................................... 70
7.4 DDR Layout Guidelines ...................................................................................................... 72
7.4.1 Source Synchronous Signal Group ....................................................................... 72
7.4.1.1
7.4.2 Clock Signal Groups .............................................................................................. 81
7.4.2.1
7.4.3 Embedded Configuration ....................................................................................... 89
7.4.3.1
7.4.3.2
7.4.3.3
7.5 DDR II 400 Layout Guidelines .......................................................................................... 101
7.5.1 Simulation Conditions .......................................................................................... 102
7.5.2 DDRII-400 Trace Width/Impedance Requirements ............................................. 103
7.5.3 DIMM Layout Design ........................................................................................... 104
7.5.3.1
7.5.3.2
7.5.3.3
7.5.4 Embedded Configuration ..................................................................................... 110
7.5.4.1
7.5.4.2
7.5.4.3
7.6 DDR Signal Termination ................................................................................................... 120
7.7 DDR Termination Voltage................................................................................................. 121
7.8 DDR V
REF
8 Peripheral Local Bus................................................................................................................. 123
8.1 Peripheral Bus Signals ..................................................................................................... 123
8.1.1 Address/Data Signal Definitions .......................................................................... 123
8.1.2 Control/Status Signal Definitions ......................................................................... 123
8.1.3 Bus Width ............................................................................................................ 124
8.1.4 Flash Memory Support ........................................................................................ 125
8.1.5 Layout Guidelines for the Peripheral Bus ............................................................ 126
8.2 Topology Layout Guidelines ............................................................................................. 127
9 Power Delivery........................................................................................................................... 131
9.1 Power Sequencing............................................................................................................ 131
9.2 Power Failure.................................................................................................................... 132
9.2.1 Theory of Operation............................................................................................. 132
9.2.2 Power Failure Sequence ..................................................................................... 132
9.2.3 Power Delay ........................................................................................................ 133
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Routing Requirements ........................................................................... 73
Control Signals Termination................................................................... 85
DDR 333 Source Synchronous Routine Guidelines .............................. 89
DDR 333 Embedded Clock Routing Recommendations ....................... 92
DDR 333 Embedded Address/Command/Control Routing Guidelines .. 96
DDR II 400 DIMM Source Synchronous Routing................................. 104
DDRII 400 Clock Routing Guidelines................................................... 107
DDRII 400 Address/Command/Control Routing Guidelines ................ 108
DDRII 400 Embedded Source Synchronous Routine Guidelines ........ 110
DDRII 400 Embedded Clock Routing Recommendations ................... 113
DDRII 400 Embedded Address/Command/Control Routing Guidelines ....
116
Voltage............................................................................................................ 121