Intel 80331 Design Manual page 13

Table 1. Terminology and Definitions (Sheet 2 of 2)
Term
Aggressor
Victim
Network
Stub
ISI
CRB
PC1600
PC2100
PC2700
PC3200
Downstream
Local memory
DWORD
Local bus
Outbound
Inbound
Local processor Intel XScale
Core processor Intel XScale
Flip Chip
Mode
Conversion
ROMB
ODT
A network that transmits a coupled signal to another network is aggressor network.
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Victim Network
Aggressor Network
A network that receives a coupled cross-talk signal from another network is a victim network.
The trace of a PCB that completes an electrical connection between two or more components.
Branch from a trunk terminating at the pad of an agent.
Intersymbol Interference (ISI). This occurs when a transition that has not been completely
dissipated, interferes with a signal being transmitted down a transmission line. ISI can impact
both the timing and signal integrity. It is dependent on frequency, time delay of the line and the
refection coefficient at the driver and receiver. Examples of ISI patterns that could be used in
testing at the maximum allowable frequencies are the sequences shown below:
Customer Reference Board
JEDEC Names for DDR based on peak data rates.
PC1600= clock of 100 MHz * 2 data words/clock * 8 bytes = 1600 MB/sec
JEDEC Names for DDR based on peak data rates.
PC2100= clock of 133 MHz * 2 data words/clock * 8 bytes = 2128 MB/sec
JEDEC Names for DDR II based on peak data rates.
PC2700= clock of 167 MHz * 2 data words/clock * 8 bytes = 2672 MB/sec
JEDEC Names for DDR II based on peak data rates.
PC3200= clock of 200 MHz * 2 data words/clock * 8 bytes = 3200 MB/sec
At or toward the Primary PCI interface from the Secondary PCI interface
Memory subsystem on the Intel XScale
busses.
32-bit data word.
80331 Internal Bus.
At or toward the PCI interface of the 80331 ATU from the Internal Bus.
At or toward the Internal Bus of the 80331 from the PCI interface of the ATU.
®
core within the 80331
®
core within the 80331
FC-BGA (flip chip-ball grid array) chip packages are designed with core flipped up on the back of
the chip, facing away from the PCB. This allows more efficient cooling of the package.
Mode Conversions are due to imperfections on the interconnect which transform differential
mode voltage to common mode voltage and common mode voltage to differential voltage.
Raid on motherboard
On Die Termination - eliminates the need for termination resistors by placing the termination at
the chip.
Intel® 80331 I/O Processor Design Guide
Definition
0101010101010101
0011001100110011
0001110001110001111
®
core DDR SDRAM or Peripheral Bus Interface
.
.
Introduction
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