Intel 80331 Design Manual page 97

Table 51. DDR 333 Embedded Address/Command Routing Recommendations (Sheet 2 of 2)
Length Matching
Number of vias
Routing Guideline 1
Parameter
Intel® 80331 I/O Processor Design Guide
Routing Guideline
• The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching
• For total capacitive loads greater than 36pF, all
ADD/CMD/CTRL trace lengths must be 2.0" to
3.0" shorter than M_CK's trace length
• For total capacitive loads less than or equal to
36pF, all ADD/CMD/CTRL trace lengths must be
1.0" to 2.0" shorter than M_CK's trace length
• For Un-buffered memory implementations:
Maximum of 5
• For Registered memory implementations:
Maximum of 5 from IOP die to register. Maximum
of 6 from Register to SDRAM.
Topology shown is based on a Raw B implementation.
Refer to JEDEC Un-buffered DIMM specs. for Raw
Card C implementation specifics.
Memory Controller
97