Jtag Hardware Requirements; Macraigor Raven And Windriver Systems Visionprobe / Visionice; Arm Multi-Ice - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
JTAG Circuitry for Debug
11.4

JTAG Hardware Requirements

Due to the conflicting requirements of Multi-ICE* and the Intel XScale
necessary to incorporate a circuit that can drive TRST# low at power up and weakly pull it high at
all other times. The following section details the circuits required for the Macraigor Raven*,
WindRiver Systems* visionPROBE* / visionICE*, and ARM* Multi-ICE*.
11.4.1 Macraigor Raven and WindRiver Systems visionPROBE /
visionICE
Both the Macraigor Raven and WindRiver Systems visionPROBE / visionICE (when configured as
active) do not require any special power-up circuitry. The requirement is that nTRST is weakly
pulled down at the processor. It is suggested that the value of the pull-down resistor is 10 KΩ or
greater. The value of this resistor needs to be confirmed with the JTAG debugger manufacturer to
ensure optimal performance.
11.4.2

ARM Multi-ICE

The ARM Multi-ICE debugger requires special power-up circuitry due to the open collector
implementation of the nTRST signal. This power-up circuit must ensure that nTRST is asserted
(low) at power on and weakly pulled high thereafter. Refer to
Power-Up Circuit for nTRST.
Figure 74. Example Power-Up Circuit for nTRST
nTRST-DGB
142
3.3 V 3.3 V
1 kΩ
3
4
0.01µF
®
Figure 74
2
MR# RESET#
220Ω
1
VCC GND
MAX811S
microarchitecture, it is
for the example of the
nTRST
A9286-01