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Intel® 80331 I/O Processor Design Guide
Contents
Figures
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1
Intel
80331 I/O Processor Functional Block Diagram............................................................... 16
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2
80331 I/O Processor 829-Ball FCBGA Package Diagram................................................ 18
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3
Intel
80331 I/O Processor Preliminary Ballout (Top View) ....................................................... 19
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4
80331 I/O Processor Preliminary Ballout (Bottom View) .................................................. 20
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5
Intel
80331 I/O Processor Power Plane Layout........................................................................ 21
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6
80331 I/O Processor PCI-X Adapter Card Block Diagram ............................................... 22
7
V
Configuration.................................................................................................................. 27
CCPLL
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8
80331 I/O Processor DDRRES Resistor Compensation Circuitry ................................... 28
9
DDR Driver Compensation Circuitry ........................................................................................... 29
10 Crosstalk Effects on Trace Distance and Height ........................................................................ 32
11 PCB Ground Layout Around Connectors ................................................................................... 33
12 Motherboard Stackup Recommendations .................................................................................. 38
13 Adapter Card Stackup ................................................................................................................ 40
14 Interrupt and IDSEL Mapping ..................................................................................................... 41
15 PCI RCOMP ............................................................................................................................... 42
16 PCI Clock Distribution and Matching Requirements................................................................... 45
17 Single-Slot Point-to-Point Topology............................................................................................ 48
18 Embedded PCI-X 133 MHz Topology ........................................................................................ 49
19 Embedded PCI-X 133 MHz Alternate Topology ......................................................................... 50
20 Embedded PCI-X 133 MHz Topology ........................................................................................ 51
21 Embedded PCI-X 133 MHz Topology ........................................................................................ 52
22 Slot PCI-X 100 MHz Slot Routing Topology ............................................................................... 53
23 Embedded PCI-X 100 MHz Routing Topology ........................................................................... 54
24 Combination of Slot and Embedded PCI-X 100 MHz Routing Topology.................................... 55
25 Combination of Slots and Embedded PCI-X 100 MHz Routing Topology .................................. 56
26 PCI-X 66 MHz Slot Routing Topology ........................................................................................ 57
27 PCI-X 66 MHz Embedded Routing Topology ............................................................................. 58
28 PCI-X 66 MHz Mixed Mode Routing Topology ........................................................................... 59
29 PCI 66 MHz Topology ................................................................................................................ 60
30 PCI 66 MHz Embedded Topology .............................................................................................. 61
31 PCI 66 MHz Mixed Topology ...................................................................................................... 62
32 PCI 33 MHz Slot Routing Topology ............................................................................................ 63
33 PCI 33 MHz Embedded Mode Routing Topology....................................................................... 64
34 PCI 33 MHz Mixed Mode Routing Topology .............................................................................. 65
35 100 ohm Differential Trace ......................................................................................................... 71
36 Source Synchronous Length Matching....................................................................................... 73
37 Data Group Length Matching ..................................................................................................... 73
38 DIMM DQ/DQS Topology ........................................................................................................... 79
39 DIMM DQ/DQS Split Termination Topology ............................................................................... 80
40 DDR 333 Registered DIMM Clock Topology .............................................................................. 83
41 DDR 333 Unbuffered DIMM Clock Topology.............................................................................. 84
42 Trace Length Requirements for Source Clocked Routing .......................................................... 85
43 DDR 333 DIMM Unbuffered/Registered Address/CMD Topology Lengths ................................ 87
44 Embedded DDR 333 DQ/DQS Topology ................................................................................... 91
45 Embedded DDR 333 Buffered Clock Topology .......................................................................... 92
46 Embedded DDR 333 Unbuffered Clock Topology ...................................................................... 95
47 Embedded DDR 333 Unbuffered ADDR/CMD Topology ........................................................... 98
48 Embedded DDR 333 Registered ADDR/CMD Topology .......................................................... 100
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