Toshiba TECRA A11 Series Maintenance Manual page 71

Troubleshooting Procedures
System BIOS IRT processing
Debug Code BIOS processing outline
F100 IRT section start
Creation of SETUP
F101
information
F102 PCI Express initialization
F103 PCH Express initialization
SMRAM Express
F104
initialization
End of SMRAM
F105
initialization
F106 EC Evart initialization
F107 USB Legacy initialization
Device Lock main
F108
processing start
Device Lock device
F109
processing start
End of Device Lock main
F10A
processing
Thermal control
F10B
initialization
Digital thermal sensor
F10C
initialization
End for IRT of a module
F10D
load
F10E Memory test start
F10F End of a memory test
F110 Interrupt vector initialization
F111 VGA, LAN initialization
End of option ROM
F112
execution
Determination of a boot
F113
device
F114 Processing in front of boot
End of IRT processing.
F115
Shift to OS.
2-28 [CONFIDENTIAL] TECRA A11/S11/P11/Satellite Pro S500 Series Maintenance Manual (960-784)
Table 2-4 Debug port error status (2/2)
Target Device
CPU
BIOSROM
RAM
PCH
PCH
PCH
RAM
PCH
RAM
EC
PCH
RAM
RAM
RAM
RAM
CPU
RAM
RAM
RAM
RAM
VGA
LAN
BIOSROM
RAM
RAM
RAM
RAM
RAM
IC No.
IS1050 (CPU Socket)
IC3000/IC3002 (BIOS ROM)
CN1400, CN1410 (RAM
Conn.)
IC1600 (PCH)
IC1600 (PCH)
IC1600 (PCH)
CN1400, CN1410 (RAM
Conn.)
IS1050 (CPU Socket),
CN1400, CN1410 (RAM
Conn.)
IC3200 (EC/KBC)
IC1600 (PCH)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
IS1050 (CPU Socket)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
IC1200 (VGA)
IC5000 (VGA (nVIDIA))
IC4000/IC4100 (LAN
Controller),
IC3000/IC3002 (BIOS
ROM), CN1400, CN1410
(RAM Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)
CN1400, CN1410 (RAM
Conn.)