Reset# (I); Rp# (I/O); Transaction Types Defined By Reqa#/Reqb# Signals; A-10 Transaction Types Defined By Reqa#/Reqb# Signals - Intel Itanium 2 Processor Datasheet
2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
Table of Contents
Advertisement
Signals Reference
All receiving agents observe the REQ[5:0]# signals to determine the transaction type and
participate in the transaction as necessary, as shown in
Table A-10. Transaction Types Defined by REQa#/REQb# Signals
Transaction
Deferred Reply
Reserved
Interrupt
Acknowledge
Special
Transactions
Reserved
Reserved
Interrupt
Purge TC
Reserved
I/O Read
I/O Write
Reserved
Memory Read &
Invalidate
Reserved
Memory Read
Memory Read
Current
Reserved
Memory Write
Cache Line
Replacement
A.1.51
RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates all caches
without writing back Modified (M state) lines. RESET# must remain asserted for one millisecond
for a "warm" reset; for a power-on reset, RESET# must stay asserted for at least one millisecond
after PWRGOOD and BCLKp have reached their proper specifications. On observing asserted
RESET#, all system bus agents must deassert their outputs within two clocks.
A number of bus signals are sampled at the asserted-to-deasserted transition of RESET# for the
power-on configuration.
Unless its outputs are tristated during power-on configuration, after asserted-to-deasserted
transition of RESET#, the processor begins program execution at the reset-vector
A.1.52
RP# (I/O)
The Request Parity (RP#) signal is driven by the requesting agent, and provides parity protection
for ADS# and REQ[5:0]#.
102
REQa[5:0]#
5
4
3
2
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
ASZ[1:0]#
0
0
ASZ[1:0]#
0
0
ASZ[1:0]#
1
1
ASZ[1:0]#
1
1
ASZ[1:0]#
1
0
ASZ[1:0]#
1
WSNP#
1
ASZ[1:0]#
1
WSNP#
Table
A-10.
1
0
5
4
0
0
0
x
0
1
0
x
0
0
0
DSZ[1:0]#
0
0
0
DSZ[1:0]#
0
0
0
DSZ[1:0]#
0
1
0
DSZ[1:0]#
0
1
0
DSZ[1:0]#
0
1
0
DSZ[1:0]#
0
1
0
DSZ[1:0]#
0
0
0
DSZ[1:0]#
0
1
0
DSZ[1:0]#
0
x
0
DSZ[1:0]#
1
0
0
DSZ[1:0]#
1
1
0
DSZ[1:0]#
D/C#
0
0
DSZ[1:0]#
0
0
0
DSZ[1:0]#
1
0
0
DSZ[1:0]#
1
0
DSZ[1:0]#
1
0
DSZ[1:0]#
REQb[5:0]#
3
2
1
0
x
x
x
x
x
x
x
x
0
0
0
0
0
1
0
1
x
0
x
x
1
0
0
1
0
1
1
1
x
x
x
x
x
x
x
x
x
x
LEN[2:0]#
LEN[2:0]#
LEN[2:0]#
LEN[2:0]#
LEN[2:0]#
LEN[2:0]#
0
0
0
Datasheet
Advertisement
Table of Contents
