Intel Itanium 2 Processor Datasheet page 7

2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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Datasheet
Processor Information ROM Format ................................................................... 82
Current Address Read SMBus Packet ................................................................ 86
Random Address Read SMBus Packet .............................................................. 86
Byte Write SMBus Packet ................................................................................... 86
Write Byte SMBus Packet ................................................................................... 87
Read Byte SMBus Packet ................................................................................... 87
Send Byte SMBus Packet ................................................................................... 87
Receive Byte SMBus Packet............................................................................... 87
ARA SMBus Packet ............................................................................................ 87
Command Byte Bit Assignment........................................................................... 88
Thermal Sensing Device Status Register............................................................ 89
Thermal Sensing Device Configuration Register ................................................ 89
Thermal Sensing Device Conversion Rate Register ........................................... 90
Address Space Size ............................................................................................ 92
Effective Memory Type Signal Encoding............................................................. 92
Special Transaction Encoding on Byte Enables.................................................. 93
BR[3:0]# Signals and Agent IDs.......................................................................... 95
DID[9:0]# Encoding ............................................................................................. 97
Extended Function Signals.................................................................................. 99
Length of Data Transfers...................................................................................100
Transaction Types Defined by REQa#/REQb# Signals ....................................102
STBp[7:0]# and STBn[7:0]# Associations .........................................................104
Output Signals...................................................................................................105
Input Signals......................................................................................................106
Input/Output Signals (Single Driver)..................................................................107
Input/Output Signals (Multiple Driver) ...............................................................107
®
2 Processor ....... 81
®
2 Processor ............................... 82
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