Electrical Specifications; Itanium ® 2 Processor System Bus; System Bus Power Pins; System Bus No Connect - Intel Itanium 2 Processor Datasheet

2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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2

Electrical Specifications

This chapter describes the electrical specifications of the Itanium 2 processor.
2.1
Itanium
Most Itanium 2 processor signals use the Itanium processor's assisted gunning transceiver logic
(AGTL+) signaling technology. The termination voltage, V
and is the system bus high reference voltage. The buffers that drive most of the system bus signals
on the Itanium 2 processor are actively driven to V
improve rise times and reduce noise. These signals should still be considered open-drain and
require termination to V
is terminated to V
which case the termination is provided by external resistors connected to V
AGTL+ inputs use differential receivers which require a reference signal (V
the receivers to determine if a signal is a logical 0 or a logical 1. The Itanium 2 processor generates
V
on-die, thereby eliminating the need for an off-chip reference voltage source.
REF
2.1.1

System Bus Power Pins

VCTERM (1.2 V) input pins on the Itanium 2 processor provide power to the driver buffers and
on-die termination. The GND pins, in addition to the GND input at the power tab connector,
provide ground to the processor. Power for the processor core is provided through the power tab
connector by V
management bus (SMBus). The V
from each other.
2.1.2

System Bus No Connect

All pins designated as "N/C" or "No Connect" must remain unconnected.
2.2

System Bus Signals

2.2.1

Signal Groups

Table 2-1
buffer type and whether they are inputs, outputs or bidirectional with respect to the processor.
Datasheet
®
2 Processor System Bus
, which provides the high level. The Itanium 2 processor system bus
CTERM
at each end of the bus. There is also support of off-die termination in
CTERM
. The 3.3 V pin is included on the processor to provide power to the system
CC,PS
CTERM
contains Itanium 2 processor system bus signals that have been combined into groups by
, is generated on the baseboard
CTERM
during a low-to-high transition to
CTERM
, 3.3 V, and GND pins must remain electrically separated
.
CTERM
). V
is used by
REF
REF
15

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