Smbus Ac Specifications - Intel Itanium 2 Processor Datasheet

Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
Symbol Parameter
T BCLKp Low Time
low
T BCLKp Period
period
T System Clock Skew
skew
f BCLKp Frequency
BCLK
T BCLKp Input Jitter
jitter
T BCLKp High Time
high
T BCLKp Low Time
low
T BCLKp Rise Time
rise
T BCLKp Fall Time
fall
V Minimum Input Swing
PP
NOTES:
1. The system clock skew is ±100 ps.
2. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn. Long term jitter is defined as peak-to-peak variation measured by
accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6. V is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
PPmin
Table 2-11. SMBus AC Specifications
Symbol
f
SMSC
T
SMSC
t
high
t
low
t
rise
t
fall
t
VALID
t
SU
t
HLD
t
FREE
NOTES:
1. Please refer to
2. Bus Free Time is the minimum time allowed between request cycles.
Datasheet
System
Bus
Minimum
Clock
(MHz)
266 1.69
333
333
333 333
333
333 1.35
333 1.35
All 333
All 333
All
Parameter
SMSC Clock Frequency
SMSC Clock Period
SMSC Clock High Time
SMSC Clock Low Time
SMSC Clock Rise Time
SMSC Clock Fall Time
SMBus Output Valid Delay
SMBus Input Setup Time
SMBus Input Hold Time
Bus Free Time
Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform.
Electrical Specifications
Typ Maximum Unit
1.88 2.06 ns
3.0 ns
60 ps
333 MHz
50 ps
1.5 1.65 ns
1.5 1.65 ns
500 667 ps
500 667 ps
600 mV
Minimum Maximum
100
10
4.0
4.7
1.0
0.3
1.0
250
0
4.7
Figure Notes
4
Figure 2-1
Figure 2-1
Figure 2-1
3
Figure 2-1
4
Figure 2-1
4
Figure 2-1
Figure 2-1 20–80%
Figure 2-1 20–80%
6
Figure 2-1
Unit Notes
kHz
µs
1
µs
1
µs
1
µs
1
µs
µs
ns
ns
2
µs
21