Summary By Model Of Msr Differences Within The - AMD -K6-2/450 - MHz Processor Application Note

23913A/0—November 2000
Table 7. Summary by Register of MSR Differences within the AMD-K6™ Family (continued)
Register
Level-2 Cache Array Access Register
Enhanced Power Management Register
Notes:
1. Standard-power versions only.
2. Low-power versions only.
Table 8. Summary by Model of MSR Differences within the AMD-K6™ Family
Standard
Model Stepping MSRs
7 All X
8 7:0 X
8 F:8 X
9 3:0 X
3:0
D X
7:4
Notes:
1. There are four MSRs that every model and stepping of the AMD-K6 family of processors support identically—MCAR, MCTR, TR12, and
TSC.
2. L2D, EWBEC, and DPE are bits/fields supported in EFER for the indicated models/steppings. All models/steppings support the System
Call Extension (SCE) bit in EFER, even if the corresponding SYSCALL and SYSRET instructions and the STAR register are not supported.
3. Indicates whether the WAELIM field supports 508 Mbytes or 4092 Mbytes of memory. The location of the WAE15M bit and the WAELIM
field within the WHCR register differs between the models/steppings that support 508 Mbytes of memory and those that support 4092
Mbytes of memory.
4. Supported on standard-power versions only.
5. Supported on low-power versions only.
Model-Specific Registers Overview
Preliminary Information
Mnemonic
L2AAR
EPMR
2
EFER
L2D EWBEC DPE SCE
1
X X
X X X
X X X
Embedded AMD-K6™ Processors BIOS Design Guide
ECX Value Models
7, 8
C000_0089h 9
D
7, 8, 9, D
C000_0086h
2
D
3
WHCR
508 4092
MB MB
STAR UWCCR
X X
X X X
X X X
X X X
X X X
Description
Not supported
page 40
page 48
1
Not supported
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PSOR
PBF
BF VID
EBF PFIR L2AAR EPMR
X X X
X X X X
4 5
X X X
X X
5
X
15