Processor State Observability Register (Psor) (Low-Power Versions); Figure 17. Processor State Observability Register (Psor) (Model D Low-Power Versions) - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide

Processor State Observability Register (PSOR) (Low-Power Versions)

63
Reserved
Symbol Description
NOL2 No L2 Functionality
STEP Processor Stepping
EBF Effective Bus Frequency Divisor

Figure 17. Processor State Observability Register (PSOR) (Model D Low-Power Versions)

PBF[2:0] Field
VID Field
46
Preliminary Information
The low-power versions of the AMD-K6-2E+ and AMD-K6-IIIE+
processors provide the Processor State Observability Register
(PSOR) as defined in Figure 17.
Note: Standard-power versions of Model D support the PSOR as
defined on page 34.
The PSOR register is MSR C000_0087h.
.
24
23
21 20
PBF[2:0]
VID
Bits
8
7-4
2-0
This read-only field contains the BF divisor values externally
applied to the processor BF[2:0] pins. These input BF values are
sampled by the processor during the falling transition of
RESET.
Note: This BF divisor value may be different than the BF divisor
value supplied to the processor's internal PLL.
This read-only field contains the Voltage ID bits driven to the
processor VID[4:0] pins at RESET. These bits are initialized to
01010b and driven on the VID[4:0] pins at RESET.
Note: Low-power AMD-K6-2E+ and AMD-K6-IIIE+ processors
support AMD PowerNow!
dynamic alteration of the processor's core voltage. See
"Enhanced Power Management Register (EPMR) (Low-
Power Versions)"
programming the VID[4:0] pins.
Symbol Description
PBF Pin Bus Frequency Divisor
VID Voltage ID
16 15
9 8
N
O
L
2
technology,
on page 54
23913A/0—November 2000
Bits
23-21
20-16
7
2
4 3 0
STEP
EBF[2:0]
which enables
for information
Model D Registers
on