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23913A/0—November 2000
31
Reserved
Symbol
Description
Tag
Tag data read or written
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
Figure 15. L2 Tag Information (AMD-K6™-III Processor)—EAX
LRU (Least Recently
Used) Field
Writing to L2 Tag of
AMD-K6™-III
Processor
Model 9 Registers
Preliminary Information
Tag
Bit
31-15
7-0
For the 4-way set associative L2 cache, each way has a 2-bit LRU
field for each sector. Values for the LRU field are 00b, 01b, 10b,
and 11b, where 00b indicates that the sector is "most recently
used," and 11b indicates that the sector is "least recently used"
(see Figure 16). EAX[7:6] indicate LRU information for Way 0,
EAX[5:4] for Way 1, EAX[3:2] for Way 2, and EAX[1:0] for
Way 3.
7
6
5
Way 0
Way 1
LRU Values
00b Most Recently Used
01b Used More Recently Than 10b, But Less Recently Than 00b
10b Used More Recently Than 11b, But Less Recently Than 01b
11b Least Recently Used
Figure 16. LRU Byte
When writing to the L2 tag of the AMD-K6-III processor, special
consideration must be given to the least significant bit of the
Tag field of the EAX register— EAX[15]. The length of the L2
tag required to support the 256-Kbyte L2 cache on the
AMD-K6-III processor is 16 bits, which corresponds to bits 31:16
of the EAX register. However, the AMD-K6-III processor
provides a total of 17 bits for storing the L2 tag—that is, 16 bits
for the tag (EAX[31:16]), plus an additional bit for internal
purposes (EAX[15]). During normal operation, the AMD-K6-III
processor ensures that this additional bit (bit 15) always
corresponds to the set in which the tag resides. Note that bits
Embedded AMD-K6™ Processors BIOS Design Guide
15
14
12
11
10 9
8
Line1ST
Line0ST
4
3
2
1
Way 2
Way 3
7
0
C
LRU
M
D
0
43
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