Quantispeed™ Architecture Summary - AMD Athlon XP 10 Datasheet

AMD Athlon™ XP Processor Model 10 Data Sheet
1.1 QuantiSpeed™ Architecture Summary
2
Preliminary Information
The features of the AMD Athlon XP processor model 10 are
QuantiSpeed™ architecture, 640 Kbytes of total, high-
performance, full-speed, on-chip cache, an advanced 400 front-
side bus (FSB) with a 3.2-Gigabyte per second system bus, or an
advanced 333 FSB with a 2.7-Gigabyte per second system bus,
and 3DNow!™ Professional technology. The AMD Athlon system
bus combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.
The AMD Athlon XP processor model 10 is binary-compatible
with existing x86 software and backwards compatible with
applications optimized for MMX™, SSE, and 3DNow! technology.
Using a data format and single-instruction multiple-data (SIMD)
o p e ra t i o n s b a s e d o n t h e M M X i n s t r u c t i o n m o d e l , t h e
AMD Athlon XP processor model 10 can produce as many as four,
32-bit, single-precision floating-point results per clock cycle. The
3 D N ow ! P ro f e s s i o n a l t e ch n o l ogy i m p l e m e n t e d i n t h e
AMD Athlon XP processor model 10 includes new integer
multimedia instructions and software-directed data movement
instructions for optimizing such applications as digital content
creation and streaming video for the internet, as well as new
i n s t r u c t i o n s fo r d i g i t a l s i g n a l p ro c e s s i n g ( D S P ) a n d
communications applications.
The following features summariz e the AMD Athlon XP
processor model 10 QuantiSpeed architecture:
An advanced nine-issue, superpipelined, superscalar x86
processor microarchitecture
instructions per cycle (IPC) and high clock frequencies
Fully pipelined floating-point unit that executes all x87
(floating-point),
Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing
high-bandwidth system capabilities
Advanced two-level translation look-aside buffer (TLB)
structures for both enhanced data and instruction address
translation. The AMD Athlon XP processor model 10 with
QuantiSpeed
optimizations: the L1 DTLB increases from 32 to 40 entries,
the L2 ITLB and L2 DTLB both use exclusive architecture,
and the TLB entries can be speculatively loaded.
Overview
designed
MMX, SSE and 3DNow! instructions
architecture incorporates
26237C—May 2003
for increased
three TLB
Chapter 1