AMD -K6-2/450 - MHz Processor Application Note page 37

23913A/0—November 2000
Model 8/[F:8] Registers
Preliminary Information
buffer operates in conjunction with the Memory Type Range
Registers (MTRRs). Refer to "UC/WC Cacheability Control
Register (UWCCR)" on page 30 for a description of the MTRRs.
Merging multiple write cycles into a single write cycle reduces
processor bus utilization and processor stalls, thereby
increasing the overall system performance.
Out-of-Order Write Cycles. The pre senc e of t he merge buf fe r
creates the potential to perform out-of-order write cycles
relative to the processor's cache. In general, the ordering of
write cycles that are driven externally on the system bus and
those that hit the processor's cache can be controlled by the
EWBE# signal. If EWBE# is sampled negated, the processor
delays the commitment of write cycles to cache lines in the
modified state or exclusive state in the processor's cache.
Therefore, the system logic can enforce strong ordering by
negating EWBE# until the external write cycle is complete,
thereby ensuring that a subsequent write cycle that hits the
cache does not complete ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor's cache. Because
these writes occur entirely within the processor and are not
sent out to the processor bus, the system logic is not able to
enforce strong ordering with the EWBE# signal.
The EWBE# control (EWBEC) bits provide a mechanism for
enforcing three different levels of write ordering in the
presence of the write merge buffer:
Best Performance. EFER[3] is defined as the Global EWBE#
Disable (GEWBED). When GEWBED equals 1, the processor
does not attempt to enforce any write ordering internally or
externally (the EWBE# signal is ignored). This is the maximum
performance setting.
Close-to-Best Performance. EFER[2] is defined as the Speculative
EWBE# Disable (SEWBED). SEWBED only af fect s the
processor when GEWBED equals 0. If GEWBED equals 0 and
SEWBED equals 1, the processor enforces strong ordering for
all internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable (UC) or
write-combining (WC) by the MTRRs. In addition, the processor
Embedded AMD-K6™ Processors BIOS Design Guide
25