Amd-K6™-2E Embedded Processor - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide
AMD-K6™-2E Embedded Processor
Model 8/[F:8]
AMD-K6™-2E+ Embedded Processor
Model D/[7:4]
4
Preliminary Information
The A M D -K 6 -2 E p ro c e s s o r a l s o s u p p o r t s t h e 3 D N ow !
instruction set and a 100-MHz processor bus.
Model 8/[F:8] is any of eight possible model/steppings—models
8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. Model 8/[F:8] is
manufactured in the 0.25-micron process.
Model 8/[F:8] implements the same six MSRs as the models
7 and 8/[7:0], but the bits and fields within two of these
MSRs—WHCR and EFER—are not defined identically.
Also, Model 8/[F:8] supports the STAR MSR and three
additional MSRs, for a total of ten MSRs.
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-2E+ processor contains a 128-
Kbyte backside L2 cache. It also supports the 3DNow! DSP
instructions extensions. Low-power versions of the processor
support AMD PowerNow!™ technology.
Model D/[7:4] is any of four possible model/steppings—models
D/4, D/5, D/6, or D/7. Model D/[7:4] is manufactured in the 0.18-
micron process.
Model D/[7:4] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically for standard-power versions. The PSOR
register is defined differently for low-power versions.
Model D/[7:4] supports an additional MSR, the Level-2
Cache Array Access Register (L2AAR), for a total of eleven
MSRs.
Low-power versions of Model D/[7:4] support an additional
MSR, the Enhanced Power Management Register (EPMR),
for a total of twelve MSRs.
23913A/0—November 2000
Processor Models and Steppings