Figure 12. L2 Cache Sector And Line Organization; Figure 13. L2 Tag Or Data Location - AMD -K6-2/450 - MHz Processor Application Note

23913A/0—November 2000
Octet 0
Octet 1
Octet 2
Octet 3

Figure 12. L2 Cache Sector and Line Organization

31
Reserved
Symbol Description
Set Selects the desired cache set
Line Selects Line1 (1) or Line0 (0)
Octet Selects one of four octets
Dword Selects upper (1) or lower (0) dword
Figure 13. L2 Tag or Data Location (AMD-K6™-III Processor)—EDX
Model 9 Registers
Preliminary Information
Upper Dword Lower Dword
Line 1
Bit 20 of EDX (T/D) determines whether the access is to the L2
cache data or tag. Table 21 on page 42 describes the operation
that is performed based on the instruction and the T/D bit.
21 20 19 18 17 16
T
Way
/
D
Bit
15-6
5
4-3
2
Embedded AMD-K6™ Processors BIOS Design Guide
Upper Dword
Sector
Symbol Description
T/D Selects Tag (1) or Data (0) access
Way Selects desired cache way
15
Set
Lower Dword
Line 0
Bit
20
17-16
6 5 4 3 2 1 0
D
L
w
i
Octet
o
n
r
e
d
41