Read-Only Memory - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide

Read-Only Memory

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Preliminary Information
sampling KEN# before it was valid (in this case, BRDY# was
used by the processor to sample KEN#). If NA# is not asserted
during memory write cycles, then the processor does not fully
take advantage of the potential performance gains that bus
pipelining can achieve.
For proper functionality, always program the WCDE bit to 0 for
models 7 and 8/[7:0]. Models 8/[F:8], 9, and D do not support the
WCDE bit.
The processor's caches must be flushed prior to defining any
area of memory as cacheable and read-only. (The BIOS is
typically "shadowed" into main memory and defined as
cacheable and read-only.) If the caches are not flushed, then a
line that resides in the processor's cache that falls within a read-
only area of memory can be written to, which would place the
cache line in the modified state. If this modified line is
subsequently replaced and written back to memory, then the
system may hang (or other unpredictable effects may occur)
because the writeback is directed to an area of memory defined
as read-only by the chipset.
23913A/0—November 2000
Additional Considerations