Figure 21. L2 Tag Or Data Location - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide
31
Reserved
Symbol Description
Set Selects the desired cache set
Line Selects Line1 (1) or Line0 (0)
Octet Selects one of four octets
Dword Selects upper (1) or lower (0) dword
Figure 20. L2 Tag or Data Location (AMD-K6™-2E+ Processor)—EDX
31
Reserved
Symbol Description
Set Selects the desired cache set
Line Selects Line1 (1) or Line0 (0)
Octet Selects one of four octets
Dword Selects upper (1) or lower (0) dword
Figure 21. L2 Tag or Data Location (AMD-K6™-IIIE+ Processor)—EDX
50
Preliminary Information
21 20 19 18 17 16 15 14
T
Way
/
D
Bit
14-6
5
4-3
2
21 20 19 18 17 16 15
T
Way
/
D
Bit
15-6
5
4-3
2
Symbol Description
T/D Selects Tag (1) or Data (0) access
Way Selects desired cache way
6
Set
Symbol Description
T/D Selects Tag (1) or Data (0) access
Way Selects desired cache way
6
Set
23913A/0—November 2000
Bit
20
17-16
5 4 3 2 1 0
D
L
w
i
Octet
o
n
r
e
d
Bit
20
17-16
5 4 3 2 1 0
D
L
w
i
Octet
o
n
r
e
d
Model D Registers