Model 9 Registers; Table 19. Model-Specific Registers Supported By Model 9 - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide

Model 9 Registers

Table 19. Model-Specific Registers Supported by Model 9

Register Name
Machine-Check Address Register
Machine-Check Type Register
Test Register 12
Time Stamp Counter
Extended Feature Enable Register
Write Handling Control Register
SYSCALL/SYSRET Target Address Regis-
ter
UC/WC Cacheability Control Register
Processor State Observability Register
Page Flush/Invalidate Register
Level-2 Cache Array Access Register
38
Preliminary Information
The AMD-K6-III processor (Model 9) provides the eleven model-
specific registers listed in Table 19.
The contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
The AMD-K6-III processor contains a split Level-1 (L1)
64-Kbyte writeback cache organized as a separate 32-Kbyte
instruction cache and a 32-Kbyte data cache with two-way set
associativity. The cache line size is 32 bytes, and lines are read
from memory using an efficient pipelined burst read cycle. In
addition, the processor also contains a 256-Kbyte, 4-way set
associative, unified level-2 (L2) cache. Further performance
gains are achieved by the implementation of a write allocation
scheme.
Mnemonic ECX Value
MCAR 00h
MCTR 01h
TR12 0Eh
TSC 10h
EFER C000_0080h
WHCR C000_0082h
STAR C000_0081h
UWCCR C000_0085h
PSOR C000_0087h
PFIR C000_0088h
L2AAR C000_0089h
23913A/0—November 2000
Description Comments
page 16 Identical on all models
page 16 Identical on all models
page 16 Identical on all models
page 16 Identical on all models
Adds L2 Disable bit (L2D) to
page 39
Model 8/[F:8] implementation
page 27 Identical to Model 8/[F:8]
page 22 Identical to Model 8/[7:0]
page 30 Identical to Model 8/[F:8]
page 34 Identical to Model 8/[F:8]
Identical to Model 8/[F:8]. The
invalidate and flush operations
page 36
affect both the L1 and L2 caches
on the AMD-K6-III processor.
page 40 New for Model 9
Model 9 Registers