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23913A/0—November 2000
AMD-K6™-III Processor
Model 9/[3:0]
AMD-K6™-IIIE+ Embedded Processor
Model D/[3:0]
Processor Models and Steppings
Preliminary Information
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-III processor contains a 256-
Kbyte backside L2 cache.
Model 9/[3:0] is any of four possible model/steppings—models
9/0, 9/1, 9/2, or 9/3. Model 9/[3:0] is manufactured in the 0.25-
micron process.
Model 9/[3:0] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically.
Model 9/[3:0] supports one additional MSR for a total of
eleven MSRs.
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-IIIE+ processor contains a 256-
Kbyte backside L2 cache. It also supports the 3DNow! DSP
instruction extensions. Low-power versions of the processor
support AMD PowerNow! technology.
Model D/[3:0] is any of four possible model/steppings—models
D/0, D/1, D/2, or D/3. Model D/[3:0] is manufactured in the 0.18-
micron process.
Model D/[3:0] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically for standard-power versions. The PSOR
register is defined differently for low-power versions.
Model D/[7:4] supports an additional MSR, the Level-2
Cache Array Access Register (L2AAR), for a total of eleven
MSRs.
Low-power versions of Model D/[7:4] support an additional
MSR, the Enhanced Power Management Register (EPMR),
for a total of twelve MSRs.
Embedded AMD-K6™ Processors BIOS Design Guide
5
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