Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 41

S86 Front Side Bus machine checks may be reported as a result of on-going
transactions during warm reset
Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the
transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset
asserts RESET# when the system is running.
Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to
occur during RESET# assertions.
BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not
Workaround:
block new transactions during RESET# assertions.
For the steppings affected, see the Summary Table of Changes.
Status:
S87 Writing the local vector table (LVT) when an interrupt is pending may cause
an unexpected interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the
new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even
if the new LVT entry has the mask bit set. If there is no interrupt service routine (ISR) set up for
that vector the system will GP fault. If the ISR does not do an end of interrupt (EOI) the bit for the
vector will be left set in the in-service register and mask all interrupts at the same or lower priority.
Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector
Workaround:
was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts
that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore
the spurious vector should not be used when writing the LVT.
For the steppings affected, see the Summary Table of Changes.
Status:
S88 The processor may issue multiple code fetches to the same cache line for
systems with slow memory
Systems with long latencies on returning code fetch data from memory, e.g. BIOS ROM, may
Problem:
cause the processor to issue multiple fetches to the same cache line, once per each instruction
executed.
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this
erratum, in a commercially available system.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
S89 CPUID feature flag reports LAHF/SAHF as unavailable, however the
execution of LAHF/SAHF may not result in an Invalid Opcode exception
As described in the IA-32 Intel Architecture Software Developer's Manual, support for
Problem:
LAHF/SAHF instructions in 64-bit mode has been added to processors with EM64T enabled. The
CPUID feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode,
even though the instructions are supported and able to be executed without an Invalid Opcode
exception.
Implication: The CPUID feature flag incorrectly reports LAHF/SAHF instructions as unavailable in 64-bit
mode, though they can be executed normally.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
41