Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 30

Errata
S38 Stores to page tables may not be visible to pagewalks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
the correct way to update page tables. Software that conforms to the Software Developer's Manual
will operate correctly.
Implication: If the guidelines in the Software Developer's Manual are not followed, stale data may be loaded
into the processor's Translation Lookaside Buffer (TLB) and used for memory operations. This
erratum has not been observed with any commercially available software.
The guidelines in the IA-32 Intel
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S39 A split store memory access may miss a data breakpoint
It is possible for a data breakpoint specified by a linear address to be missed during a split store
Problem:
memory access. The problem can happen with or without paging enabled.
Implication: This erratum may limit the debug capability of a debugger software.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S40 EFLAGS.RF may be incorrectly set after an IRET instruction
EFLAGS.RF is used to disable code breakpoints. After an IRET instruction, EFLAGS.RF may be
Problem:
incorrectly set or not set depending on its value right before the IRET instruction.
Implication: A code breakpoint may be missed or an additional code breakpoint may be taken on next
instruction.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S41 Writing the Echo TPR disable bit in IA32_MISC_ENABLE may cause a #GP
fault
Writing a '1' to the Echo TPR disable bit (bit 23) in IA32_MISC_ENABLE may incorrectly cause
Problem:
a #GP fault.
Implication: A #GP fault may occur if the bit is set to a '1'.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S42 Incorrect access controls to MSR_LASTBRANCH_0_FROM_LIP MSR
registers
Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected
#GP fault may not happen.
Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
30
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Architecture Software Developer's Manual for
®
Architecture Software Developer's Manual should be followed.
®
64-bit Intel Xeon
(1 MB and 2 MB L2 Cache Versions) Specification Update
®
Processor with 800 MHz System Bus