Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 20

Errata
accesses data that splits across a page boundary with both pages of WB memory type. The
use-once protocol activates and the memory type for the split halves get forced to UC. Since
use-once does not apply to stores, the store unlock instructions go out as WB memory type. The
full sequence on the Bus is: locked partial read (UC), partial read (UC), partial write (WB), locked
partial write (WB). The Use-once protocol should not be applied to Load locks.
When this erratum occurs, the memory type of the load lock will be different than the memory type
Implication:
of the store unlock operation. This behavior (Load Locks and Store Unlocks having different
memory types) does not however introduce any functional failures such as system hangs or
memory corruption.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S5 Machine Check Architecture error reporting and recovery may not work as
expected
When the processor detects errors it should attempt to report and/or recover from the error. In the
Problem:
situations described below, the processor does not report and/or recover from the error(s) as
intended.
•
When a transaction is deferred during the snoop phase and subsequently receives a Hard
Failure response, the transaction should be removed from the bus queue so that the processor
may proceed. Instead, the transaction is not properly removed from the bus queue, the bus
queue is blocked, and the processor will hang.
•
When a hardware prefetch results in an uncorrectable tag error in the L2 cache,
MC0_STATUS.UNCOR and MC0_STATUS.PCC are set but no machine check exception
(MCE) is signaled. No data loss or corruption occurs because the data being prefetched has not
been used. If the data location with the uncorrectable tag error is subsequently accessed, an
MCE will occur. However, upon this MCE, or any other subsequent MCE, the information for
that error will not be logged because MC0_STATUS.UNCOR has already been set and the
MCA status registers will not contain information about the error which caused the MCE
assertion but instead will contain information about the prefetch error event.
•
When the reporting of errors is disabled for machine check architecture (MCA) Bank 2 by
setting all MC2_CTL register bits to 0, uncorrectable errors should be logged in the
IA32_MC2_STATUS register but no machine-check exception should be generated.
Uncorrectable loads on bank 2, which would normally be logged in the IA32_MC2_STATUS
register, are not logged.
•
When one half of a 64 byte instruction fetch from the L2 cache has an uncorrectable error and
the other 32 byte half of the same fetch from the L2 cache has a correctable error, the processor
will attempt to correct the correctable error but cannot proceed due to the uncorrectable error.
When this occurs the processor will hang.
•
When an L1 cache parity error occurs, the cache controller logic should write the physical
address of the data memory location that produced that error into the IA32_MC1_ADDR
REGISTER (MC1_ADDR). In some instances of a parity error on a load operation that hits
the L1 cache, however, the cache controller logic may write the physical address from a
subsequent load or store operation into the IA32_MC1_ADDR register.
•
When an error exists in the tag field of a cache line such that a request for ownership (RFO)
issued by the processor hits multiple tag fields in the L2 cache (the correct tag and the tag with
the error) and the accessed data also has a correctable error, the processor will correctly log the
multiple tag match error but will hang when attempting to execute the MCE handler.
•
If a memory access receives a machine check error on both 64 byte halves of a 128-byte L2
cache sector, the IA32_MC0_STATUS register records this event as multiple errors, i.e., the
valid error bit and the overflow error bit are both set indicating that a machine check error
20
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update