Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 26

Errata
S20 A 16-bit address wrap resulting from a near branch (jump or call) may cause
an incorrect address to be reported to the #GP exception handler
Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address
outside of the code segment, the address of the branch instruction should be provided to the general
protection exception handler. It is possible that, as a result of this erratum, that the general
protection handler may be called with the address of the branch target.
Implication: A 16-bit software environment which is affected by this erratum, will see that the address reported
by the exception handler points to the target of the branch, rather than the address of the branch
instruction.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S21 Bus locks and SMC detection may cause the processor to temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor
executes a synchronization loop that includes one or more bus locks and is waiting for release by
the other logical processor. If the releasing logical processor is executing instructions that are
within the detection range of the self-modifying code (SMC) logic, then the processor may be
locked in the synchronization loop until the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S22 Incorrect physical address size returned by CPUID instruction
The CPUID instruction Function 80000008H (Extended Address Sizes Function) returns the
Problem:
address sizes supported by the processor in the EAX register. This Function returns an incorrect
physical address size value of 40 bits. The correct physical address size is 36 bits.
Implication: Function 80000008H returns an incorrect physical address size value of 40 bits.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S23 Incorrect debug exception (#DB) may occur when a data breakpoint is set
on an FP instruction
The default microcode floating-point event handler routine executes a series of loads to obtain data
Problem:
about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction
causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in
a debug exception.
Implication: An incorrect debug exception (#DB) may occur if data breakpoint is placed on an FP instruction.
Intel has not observed this erratum with any commercially available software or system.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S24 xAPIC may not report some illegal vector errors
The local xAPIC has an error status register, which records all errors it detects. Bit 6 of this
Problem:
register, the receive Illegal Vector bit, is set when the local xAPIC detects an illegal vector in a
message that it receives. When an illegal vector error is received on the same internal clock that the
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64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update