Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 17

Errata (Sheet 5 of 5)
D-0/ E-0/
No.
0F34h 0F41h 0F49h
S81 X X
S82 X X
S83 X X
S84 X X
S85 X X
S86 X X
S87 X X
S88 X X
S89
S90 X X
S91 X
S1S X X
S92 X X
S93 X X
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
G-1/ N-0/ R-0/
Plans
0F43h 0F4Ah
X X X Plan Fix
X X X No Fix
X X X Plan Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X Plan Fix
X X X No Fix
Fixed
X X X NoFix
X X X No Fix
X X X No Fix
Summary Table of Changes
Errata
Running in System Management Mode (SMM) and L1 data
cache adaptive mode may cause unexpected system
behavior when SMRAM is mapped to cacheable memory
A 64-bit value of Linear Instruction Pointer (LIP) may be
reported incorrectly in the Branch Trace Store (BTS) memory
record or in the Precise Event Based Sampling (PEBS)
memory record
It is possible that two specific invalid opcodes may cause
unexpected memory accesses
At core-to-bus ratios of 16:1 and above Defer Reply
transactions with non-zero REQb values may cause a Front
Side Bus stall
Processor may issue Frost Side Bus transactions up to 6
clocks after RESET# is asserted
Front Side Bus machine checks may be reported as a result
of on-going transactions during warm reset
Writing the local vector table (LVT) when an interrupt is
pending may cause an unexpected interrupt
The processor may issue multiple code fetches to the same
cache line for systems with slow memory
CPUID feature flag reports LAHF/SAHF as unavailable,
however the execution of LAHF/SAHF may not result in an
Invalid Opcode exception
IRET under certain conditions may cause an unexpected
Alignment Check Exception
Upper 32 bits of 'From' address reported through LBR or LER
MSRs, BTMs or BTSs may be incorrect
EXTEST/CLAMP may cause incorrect values to be driven on
processor pins
The IA32_MC0_STATUS/IA32_MC1_STATUS/
IA32_MC4_STATUS Overflow Bit is not set when multiple
un-correctable machine check errors occur at the same time.
Debug Status Register (DR6) Breakpoint Condition Detected
Flags May be Set Incorrectly.
17