Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 38

Errata
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
Status: For the steppings affected, see the Summary of Changes.
S75 Memory ordering failure may occur with snoop filtering third-party agents
after issuing and completing a BWIL (Bus Write Invalidate Line) or BLW
(Bus Locked Write) transaction
Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW
transaction, retain data from the addressed cache line in shared state even though the specification
requires complete invalidation. This data retention may also occur when a BWIL transaction's
self-snooping yields HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates coherence
sequencing which depends on a full self-invalidation of the cache line associated with (1) BWIL
and BLW transactions, or (2) all HITM snoop results without regard to the transaction type and
snoop results' source.
1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read
Workaround:
Invalidate Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or
BLW) transaction to insure complete validation of the associated cache line. If there are no
intervening processor-originated transactions to that cache line, the central agent's invalidating
snoop will get a clean snoop result. Or,
2. Snoop filtering central agents can:
a. Not use processor-originated BWIL or BLW transactions to update their snoop filter
information, or
b. Update the associated cache line state information to shared state on the originating bus
(rather than invalid state) in reaction to a BWIL or BLW.
For the steppings affected, see the Summary Table of Changes.
Status:
S76 Control Register 2 (CR2) can be updated during a REP MOVS/STOS
instruction with fast strings enabled
Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast
Problem:
strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging
event, normally invisible to the user. Any higher priority architectural event that arrives and is
handled while the interim paging event is occuring may see the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not
observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes at the beginning of this section.
Status:
S77 REP STOS/MOVS instructions with RCX >= 2^32 may cause system hang
In IA-32e mode using Intel EM64T-enabled processors, executing a repeating string instruction
Problem:
with the iteration count greater than or equal to 2^32 and a pending event may cause the REP
STOS/MOVS instruction to live lock and hang.
Implication: When this erratum occurs, the processor may live lock and result in a system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: Do not use strings larger than 4 GB.
For the steppings affected, see the Summary Table of Changes.
Status:
38
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64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update