Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 36

Errata
For the steppings affected, see the Summary Table of Changes.
Status:
S67 IA32_MCi_STATUS MSR may improperly indicate that additional MCA
information may have been captured
When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the
Problem:
IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR
and IA32_MCi_MISC MSRs were not properly captured.
Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC registers may not correspond to the reported machine-check error, even though
the ADDRV and MISCV are asserted.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S68 With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP
Exception may take single step trap before retirement of instruction
If an FP instruction generates an unmasked exception with the EFLAGS.TF = 1, it is possible for
Problem:
external events to occur, including a transition to a lower power state. When resuming from a lower
power state, it may be possible to take the single step trap before the execution of the original FP
instruction completes.
Implication: When this erratum occurs, a single step trap will be taken unexpectedly.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S69 PDE/PTE loads and continuous locked updates to the same cache line may
cause system livelock
In a multi-processor configuration, if one processor is continuously doing locked updates to a
Problem:
cache line that is being accessed by another processor doing a page table walk, the page table walk
may not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S70 MCA-corrected memory hierarchy error counter may not increment
correctly
An MCA-corrected memory hierarchy error counter can report a maximum of 255 errors. Due to
Problem:
the incorrect increment of the counter, the number of errors reported may be incorrect.
Due to this erratum, the MCA counter may report an incorrect number of soft errors.
Implication:
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S71 Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may
update memory outside the BTS/PEBS buffer
If the BTS/PEBS buffer is defined such that:
Problem:
1. The difference between the BTS/PEBS buffer base and the BTS/PEBS absolute maximum is
not an integer multiple of the corresponding record sizes,
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64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update