Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 39

S78 REP MOVS or REP STOS instruction with RCX >= 2^32 may fail to execute
to completion or may write to incorrect memory locations on processors
supporting Intel
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS
instruction executed with the register RCX >= 2^32, may fail to execute to completion or may
write data to incorrect memory locations.
Implication: This erratum may cause incomplete instruction execution or incorrect data in the memory. Intel has
not observed this erratum with any commercially available software.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S79 An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX
>= 2^32 may cause a system hang on processors supporting Intel
Extended Memory 64 Technology (Intel
In IA-32e mode using Intel EM64T-enabled processors, a REP LOSDB or an REP LODSD or an
Problem:
REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution
causing a system hang. Additionally, there may be no #GP fault due to the non-canonical address in
the RSI register.
Implication: This erratum may cause a system hang on Intel EM64T-enabled platforms. Intel has not observed
this erratum with any commercially available software.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S80 Data access which spans both canonical and non-canonical address space
may hang system
If a data access causes a page split across the canonical to non-canonical address space, the
Problem:
processor may livelock which in turn would cause a system hang.
Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not
observed this erratum with any commercially available software.
None identified.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S81 Running in System Management Mode (SMM) and L1 data cache adaptive
mode may cause unexpected system behavior when SMRAM is mapped to
cacheable memory
In a HT Technology-enabled system, unexpected system behavior may occur if a change is made to
Problem:
the value of the CR3 result from an Resume from System Management (RSM) instruction while in
L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will
only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit.
Implication: This erratum can have multiple failure symptoms, including incorrect data in memory. Intel has not
observed this erratum with any commercially available software.
Workaround: Disable L1 data cache adaptive mode by setting the L1 data cache context mode control bit (bit 24)
of the IA32_MISC_ENABLES MSR (0x1a0) to 1.
For the steppings affected, see the Summary Table of Changes.
Status:
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
®
Extended Memory 64 Technology (Intel
®
EM64T)
®
EM64T)
Errata
®
39